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Chip Design

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Samsung Reports Prototype 900‑Layer V‑NAND Chip

Built by bonding two 450‑layer wafers with Cell Multi‑Bonding, the prototype could raise per‑chip capacity if it clears production and cost hurdles.

Synopsys Faces First Post‑Ansys Earnings Test After Market Close

Cadence Lifts 2026 Sales Outlook After Q1 Beat, Cuts EPS Guidance

Anker Unveils THUS, a Compute-in-Memory AI Chip for Tiny Devices

SK Hynix Files Record $8 Billion Order for ASML EUV Tools for 2027 Delivery

ASML Sets Course Beyond EUV With Packaging Tools as High‑NA Progresses

NIO’s Chip Unit Anhui Shenji Raises Over RMB 2.2 Billion at Near-RMB 10 Billion Valuation

Tesla Revives Dojo 3 as Musk Says AI5 Design Nears Finish, Sets Nine‑Month Chip Cadence

India Launches DHRUV64, a 1.0 GHz Homegrown 64-Bit Dual-Core RISC-V Chip

Intel Returns to Profit as 18A Hits High-Volume Output and Supply Tightens

Swiss Startup Chipmind Launches AI Agents for Chip Design, Raises $2.5 Million

Chinese Researchers Report All‑Frequency 6G Chip Hitting 100 Gbps in Lab Tests

SK hynix Begins Mass Production of 321-Layer 2Tb QLC NAND

Qualcomm’s Snapdragon W5 Gen 2 Brings Satellite SOS to Wear OS as Pixel Watch 4 Debuts the Chip

Lightmatter and Lightelligence Showcase Photonic Chips for AI Processing

NVIDIA Envisions Future AI Chips with 3D GPU Stacking and Silicon Photonics

Nvidia's Blackwell AI Chips Delayed by Design Flaws