Overview
- Synopsys demonstrated the new long‑running, fully autonomous design verification and CAE workflows at the Design Automation Conference on Monday and said customers are now evaluating the tools.
- The company reported its verification orchestrator can compress weeks of manual work into hours, claiming up to 50X faster time‑to‑validated RTL and about 20% improved verification coverage.
- Synopsys said its autonomous analog and mixed‑signal flows use AI‑powered layout synthesis to boost analog engineering productivity by up to 3X and to automate multi‑step implementation and verification.
- The agentic flows and a more than 20‑product GPU acceleration push rely on NVIDIA technologies and CUDA‑X libraries, with reported speedups such as PrimeSim SPICE ~18X, QuantumATK up to 50X (and up to 200X for learned force‑field runs), and Ansys Lumerical FDTD ~10X on GPUs.
- The rollout is framed by a wider company shift toward AI tooling and integration of Ansys assets, which could speed design cycles for adopters but also requires customers to manage transitions from some legacy factory analytics and workflows.