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Perlmutter Nears Full Capacity to Simulate Next-Gen Quantum Chip in Full-Wave Detail

Using the ARTEMIS modeling tool, the run aims to vet designs before fabrication, with frequency-domain benchmarks and lab validation planned next.

Overview

  • The team leveraged nearly all 7,168 NVIDIA GPUs on NERSC’s Perlmutter, discretizing a 10 mm by 10 mm chip into 11 billion grid cells.
  • More than a million time steps completed in about seven hours enabled evaluation of three circuit configurations within a single day.
  • The simulation used physics-grounded, time-domain full-wave modeling that captured materials, wiring, resonator geometry, and nonlinear electromagnetic interactions.
  • Researchers from Berkeley Lab and UC Berkeley led the effort with QSA and AQT, modeling a device designed by Irfan Siddiqi’s Quantum Nanoelectronics Laboratory.
  • NERSC engineers called it one of Perlmutter’s most ambitious quantum projects, and the team will next conduct quantitative, frequency-domain studies and compare results with a fabricated chip, with highlights slated for SC25.