Overview

• Revealed at Semicon India 2025 in New Delhi, the processor was presented to Prime Minister Narendra Modi by Union Minister Ashwini Vaishnaw.
• Developed by ISRO’s Vikram Sarabhai Space Centre with fabrication at the Semiconductor Laboratory in Chandigarh on 180 nm CMOS, it succeeds the 16‑bit Vikram‑1601 used on launch vehicles since 2009.
• Specifications include a 100 MHz 32‑bit core running on a single 3.3 V supply, operating power under 500 mW, a −55°C to 125°C range, built‑in test features, and a 181‑pin CPGA package with dual MIL‑STD‑1553B interfaces.
• The processor employs a custom instruction set oriented to the Ada language with floating‑point capability, and ISRO built its compiler, simulator, and IDE in‑house.
• ISRO confirms initial devices were flight‑validated on the PSLV‑C60 POEM‑4 module, and reports suggest potential use on upcoming missions remains unconfirmed.