Overview
- The government formally notified Semicon 2.0 on Monday, August 31, launching a ₹1,27,500 crore programme that covers six pillars across the chip value chain.
- For silicon wafer fabs the Centre will fund up to 40% of eligible capital expenditure for projects that commit at least ₹20,000 crore and meet technical and revenue thresholds.
- The design pillar creates two tracks: a strategic category where IP must remain in India and will be co‑owned with C‑DAC, and a commercial track offering seed grants, equity co‑investment and a 9% deployment incentive for new chips.
- New support targets equipment, materials and testing with up to 30% capex aid plus production‑linked incentives, while R&D and talent projects can receive up to 75% of costs and a target to train 100,000 more semiconductor engineers.
- The India Semiconductor Mission will run the scheme, applications are open for three years, projects above set limits need higher approvals, and a three‑year mid‑term review will assess progress and adjustments.