Overview
- IBM on Thursday, June 25, 2026, presented a research prototype it calls a 0.7 nm (7‑angstrom) node built with a new three‑dimensional “nanostack” transistor architecture.
- The nanostack stacks and staggers nanosheet transistors across bonded wafers and was experimentally validated with ultra‑thin dielectric bonding, dual‑channel engineering and working CMOS inverters.
- IBM says the design packs nearly 100 billion transistors onto a fingernail‑sized die and yields a 40% reduction in SRAM cell area versus its 2 nm work, improving on‑chip memory density important for AI workloads.
- Published projections from IBM put the 0.7 nm node at up to 50% higher performance or up to 70% better energy efficiency versus its 2 nm technology, figures that could lower data‑center power costs if realized in production.
- The result is a lab milestone not a shipping product; IBM expects a production path of roughly five years and depends on equipment and process partners including ASML, Lam Research, Tokyo Electron and SCREEN plus foundry adoption and qualification.