Overview
- IBM unveiled the dual‑ISA processor design at Hot Chips on Monday, August 24, describing cores that natively implement both z/Architecture and AArch64 so the same core can execute either instruction set.
- The chip is described as a 2 nanometer design with 11 high‑performance cores running above 5.7 GHz, large multi‑level caches, on‑chip AI inference accelerators and a dedicated data processing unit for I/O acceleration.
- IBM said each core can switch between ISAs in nanoseconds and run Arm virtual machines without software changes by using kernel‑level virtualization for AArch64 while preserving native z/Architecture execution.
- Alongside the CPU, IBM showed a next‑generation AI accelerator that uses 96 GB of HBM3e to deliver much higher memory bandwidth for larger AI inference workloads than prior LPDDR5 designs.
- The company framed the chip as the first hardware milestone from its April collaboration with Arm, but stressed the design remains under development, no ship date was announced, and market reaction to the reveal was modestly negative for Arm and flat to slightly down for IBM.