Overview
- IBM unveiled the processor at the Hot Chips conference on Monday, August 24, 2026, and disclosed the design is being sent to tape for fabrication with no customer ship date.
- Each of the chip’s 11 high-performance cores is engineered to natively execute both IBM z/Architecture and AArch64 (Arm) instructions and to switch between them in nanoseconds.
- The design uses a 2 nanometer process, targets base clocks above 5.7 GHz, and layers a large private L2 with virtual L3/L4 caches to support transaction and data-heavy workloads.
- IBM built multiple on-chip accelerators into the silicon, including AI inference blocks for in-transaction fraud detection, a dedicated DPU for I/O acceleration, and hardware for compression and cryptography.
- If realized at scale, the chip would let enterprises run Arm-native VMs and the Arm software ecosystem directly on mainframes next to z/OS workloads, a change that could reduce porting and virtualization friction for banks and regulated industries while requiring years of validation before broad deployment.