Overview
- IBM unveiled the technology on Thursday, June 25, saying its new three‑dimensional 'nanostack' stacks transistors vertically to reach a 0.7 nanometer (7‑angstrom) architecture.
- IBM says the design can fit nearly 100 billion transistors on a fingernail‑sized die and projects up to 50% higher performance or 70% better energy efficiency versus its 2 nm chips.
- A Nature paper from University of Illinois researchers published May 30 reported a low‑temperature method using 10 nm silicon nanomembranes to stack layers with 98–100% device yields in three‑layer demonstrations, supporting the feasibility of 3D integration in labs.
- Commercial use remains uncertain because IBM has not named a manufacturing partner and must prove the design at fab scale, while rivals press ahead with their own nodes, including Intel moving its 18A (1.8 nm) process into risk production.
- If scaled successfully, the combination of nanostack design and low‑temperature 3D stacking could extend transistor scaling for AI workloads by raising density and cutting power per operation, but key hurdles include thermal budgets, packaging, and securing foundry capacity.