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Huawei Pulls Forward Ascend 960 Launch and Unveils SuperPod and Interconnect Plan

The company says faster Ascend chips plus new UnifiedBus/Peerium networking aim to stitch thousands of processors into giant clusters to narrow the gap with Nvidia and reduce reliance on foreign silicon.

Visitors past by the Huawei booth display of the Atlas 950 SuperPoD during the World AI Conference in Shanghai, China on Friday, July 17, 2026. (AP Photo/Ng Han Guan)
People walk past the Huawei booth, where the Atlas 950 SuperPoD system is displayed, during the World Artificial Intelligence Conference (WAIC) in Shanghai, China, July 17, 2026. REUTERS/Go Nakamura/File Photo
The Huawei logo at the World Artificial Intelligence Conference (WAIC) in Shanghai, China, July 17, 2026. REUTERS/Go Nakamura/File Photo
FILE -Visitors stand near the Huawei Atlas 950 SuperPod during the World AI Conference in Shanghai, Friday, July 17, 2026. (AP Photo/Ng Han Guan, File)

Overview

  • Huawei announced at its Huawei Connect conference on Sept. 17 that it has moved the Ascend 960DT launch to Q1 2027 and the Ascend 960PR to Q3 2027, saying the chip timetable is running ahead of prior plans.
  • The firm introduced the Atlas 960 SuperPoD and detailed UnifiedBus and Peerium architectures that it says will link supernodes into very large clusters, with company claims of scaling up to one million processors over multiple generations.
  • Huawei said production capacity cannot meet domestic demand and that it will prioritize Chinese customers, a constraint the company says limits any major overseas sales for now.
  • The company reported operational traction with more than 1,000 shipped supernodes and about 5,200 monthly active developers on its Ascend ecosystem, but analysts note Nvidia still holds a software and developer lead with tools like CUDA.
  • If Huawei delivers the timeline and interconnects it described, the move could shift where Chinese AI models are trained and speed China’s chip self-reliance, though hardware bottlenecks such as advanced memory and manufacturing access remain potential obstacles.