Overview
- Micron told Hot Chips on Aug. 23 that compute performance is scaling about 3× every two years while HBM bandwidth grows at under 2×, a divergence the company called a worsening memory wall that leaves many AI workloads memory‑bound.
- JEDEC raised the HBM package thickness ceiling to 775 microns but vendors reported that this limit and shrinking die gaps mean MR‑MUF packaging is near its practical margin for taller stacks.
- SK hynix said hybrid Cu‑Cu bonding is not expected to be ready for HBM4E and pushed earliest realistic adoption to HBM5, making hybrid bonding a multi‑year prospect rather than an immediate fix.
- Manufacturers described near‑term engineering responses shown at Hot Chips that include moving the HBM base die to logic process nodes to cut power and reclaim area, adding localized hotspot cooling blocks, and refining MR‑MUF techniques.
- The industry warned that HBM’s wafer‑area penalty — Micron estimates roughly three times the silicon area of DDR5 for equal capacity — is raising per‑bit costs and helping drive the DRAM price and supply pressure that have pushed up PC and server memory prices.