Particle.news

CXMT Says It Will Ship 4F² DDR5 Server Memory by Year‑End

If proven at manufacturing scale, the company’s vertical‑channel 4F² cell could materially raise density and shift competitive pressure onto established memory makers.

Overview

  • CXMT President Cao Kanyu told a Shanghai industry conference on Oct. 11 that the company intends to ship a DDR5 RDIMM using a 4F² DRAM cell architecture before the end of 2026.
  • The firm claims the 4F² design, driven by an in‑house Vertical Surrounded Gate transistor and High‑k Metal Gate process, can boost cell density roughly 30–50 percent versus today’s 6F² layout.
  • Global memory stocks plunged after the announcement, with Micron down about 3.6 percent and Samsung and SK Hynix falling more than 7 percent in South Korean trading as the KOSPI dropped roughly 6 percent.
  • Key details remain undisclosed and unverified: independent lab confirmation, production yields, full product specifications and customer qualification are all needed before commercial impact can be judged.
  • CXMT points to published research since 2021, hundreds of patent families and an aggressive wafer‑capacity target of about 300,000 wafers per month by year‑end as the basis for its claim, while incumbents expect 4F² mass production later, around 2028 for Samsung.