Overview
- AMD announced the EPYC 9006 'Venice' series as its first Zen 6 server chips with production begun this year and OEM availability slated for Q4 2026.
- Zen 6 densifies each chiplet to 12 full‑performance cores with 48 MB of shared L3 cache and AMD reports about a 27 percent geometric‑mean IPC uplift for the denser Zen 6c variant.
- The family is split into specialized lines: Venice host nodes, Venice‑X with stacked 3D V‑Cache for memory‑sensitive HPC, Verano (EPYC 9006 LP) for power‑efficient agentic AI with LPDDR5X SOCAMM2 support, and long‑life Embedded SKUs with up to 256 cores and seven years of availability.
- Platform advances include TSMC 2 nm manufacturing, PCIe Gen6 and up to 1.6 TB/s per‑socket memory bandwidth on SP7 systems, and AMD also highlighted built‑in security features such as a silicon root of trust and post‑quantum firmware signing.
- Coverage on Nov. 10, 2026 added technical slides and variant plans showing Venice‑X will appear in 2H 2027 and some embedded SKUs are scheduled to ship in November–December 2026, setting up a phased rollout through 2027.